1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of an interconnection requiring the provision of a barrier layer between a bulk metal and a dielectric in which the interconnection is embedded.
2. Description of the Related Art
In an integrated circuit, a huge number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of many modern integrated circuits, generally, the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but such electrical connections may be established in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnections.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the package density, also increases, thereby usually requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of up to twelve stacked metallization layers that are required, for example, for sophisticated aluminum-based microprocessors, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows reduction of the dimensions of the interconnections and thus the number of metallization layers. For example, copper is a metal generally considered to be a viable candidate for replacing aluminum due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum.
In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used wherein a dielectric layer is first blanket-deposited and then patterned to define trenches and vias, which are subsequently filled with copper. A further major drawback of copper is its property to readily diffuse in silicon dioxide and other low-k dielectrics.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially reduce diffusion of copper into the surrounding dielectric material, as copper may readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. The barrier material provided between the copper and the dielectric material should, however, in addition to the required barrier characteristics, exhibit good adhesion to the dielectric material as well as to the copper and should also have as low an electrical resistance as possible so as to not unduly compromise the electrical properties of the interconnection. In typical copper-based applications, tantalum and tantalum nitride, alone or in combination, as well as titanium and titanium nitride, alone or in combination, may successfully be employed as barrier layers. However, any other barrier layer schemes may be used as long as the required electrical, diffusion hindering and adhesion characteristics are obtained.
Irrespective of the material used for the barrier layer, with steadily decreasing feature sizes, process engineers are increasingly confronted with the challenging task to deposit an extremely thin barrier layer within trenches and vias having significantly high aspect ratios of approximately 5 or more for a trench width or a via diameter of about 0.2 μm and even less. The thickness of the barrier layer has to be chosen as thin as possible to not unduly consume space that would otherwise be occupied by the interconnection that should be filled with the more conductive copper, yet reliably suppressing or preventing the diffusion of the copper into the neighboring dielectric. The deposition of the barrier material within high aspect ratio vias, especially on sidewalls of lower portions of the vias, requires improved techniques for physical vapor deposition (PVD) processes. PVD processes are frequently used in depositing conductive materials on a substrate because of the enhanced directionality of the target atoms sputtered off an appropriate target, which is useful in directing target atoms to the bottom of the vias.
For example, in “Thin, High Atomic Weight Refractory Film Deposition for Diffusion Barrier, Adhesion Layer and Seed Layer Applications,” by Rossnagel et al., J. Vac. Sci. Technol., May/June 1996, a method is disclosed to deposit tantalum atoms on steep via and trench sidewalls by employing conventional non-collimated sputter deposition at very low pressures to achieve the improved directionality of the tantalum atoms.
In U.S. Pat. No. 6,306,732 to Brown, a method is suggested for improving the directionality of the target atoms, wherein an ionized PVD (IPVD) process is employed in combination with a subsequent re-sputtering step. In the ionized sputter process, a specified fraction of the target atoms (and of carrier and precursor gases if provided) is ionized by any appropriate means and a bias voltage is established between the ionized atoms and the substrate to guide the atoms to the substrate, wherein a distance between the target and substrate may be increased compared to conventional sputter tools. Due to the improved directionality of the target atoms, the bottom coverage of even very narrow and deep vias is excellent, whereas the sidewall coverage, especially in the vicinity of the bottom corners, is poor. The subsequent re-sputter step allows removal of a fraction or substantially all of the material formed on the bottom and to redistribute the material preferably at the lower sidewall portions.
Although these methods show a significant improvement over standard sputter processes, the former method suffers from a reduced barrier layer thickness at the sidewalls of the via, requiring an unduly long deposition time, thereby creating a disproportional thickness at the bottom thereof, while the latter method exhibits a remarkable sensitivity to even small variations in the structure of the via or trench. For instance, varying dimensions, different sidewall angles or, in worst-case structure irregularities, such as fencing at the via opening, minor protrusions within the trench and via, and the like may lead to reduced and thus insufficient coverage at certain portions within the trench and/or via.
In view of the above-identified difficulties encountered by the known methods, a need exists for an enhanced technique that enables material deposition on the basis of re-sputter techniques while preventing or at least reducing one or more of the above-identified problems.